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NCP5030 Buck-Boost Converter to Drive a Single LED from 1 Li-Ion or 3 Alkaline Batteries
The NCP5030 is a fixed frequency PWM buck-boost converter optimized for constant current applications such as driving high-powered white LED. The buck-boost is implemented in an H-bridge topology and has an adaptive architecture where it operates in one of three modes: boost, buck-boost, or buck depending on the input and output voltage condition. This device has been designed with high-efficiency for use in portable applications and is capable of driving in DC up to 900 mA into a high power LED for flashlight / torch applications. To protect the device cycle-by-cycle current limiting and a thermal shutdown circuit have been incorporated as well as output over-voltage protection. The 700 kHz switching frequency allows the use of a low value 4.7 mH and ceramic capacitors. The NCP5030 is housed in a low profile space efficient 3x4 mm thermally enhanced WDFN.
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MARKING DIAGRAM
1
1 WDFN12 3x4 MT SUFFIX CASE 506AY
5030 ALYWG G
* * * * * * *
Efficiency: 87% at 500 mA and 3.3 V VIN Internal Synchronous Rectifier, No Schottky Diodes Adjustable Switching Limit Current to Optimize inductor size 0.3 mA Shut-down Control with "True-Cut off" Input Voltage Range from 2.7 V to 5.5 V 200 mV Feedback Voltage Output Over-voltage and Thermal Shut Down Protection
5030 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
PIN CONNECTIONS
FB COMP CTRL PVIN 1 2 3 13 4 5 6 (Top View) D1 Exposed pad (Pin 13) is PGND must be soldered to PCB GND plane 12 11 10 9 8 7 PCA AGND VIN VS VOUT LX2
Typical Applications
* Portable Flashlight / Torch Lights
Vin 1 Cell Li-Ion 2.7 to 5.5 39 k R1 ENABLE AGND CTRL PCA COMP FB PGND C2 10 mF Cin 1 mF VIN 4.7 mH L1
LX1 LX1
Cin LX1 LX1 PVIN
LX2
C3 22 mF VS Cout
VOUT
NCP5030
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
L1: TDK RLF7030T-4R7M3R4 C1: 1 mF 6.3 V X5R C2: 10 mF 3.6 V 0805 TDK: C2012X5R0J106MT C4 C3: 22 mF 6.3 V X5R 22 pF TDK: C2012X5R0J226MTJ
R2 100 k C5 330 pF
R3 220 m RSENSE
Figure 1. Typical Application Circuit
(c) Semiconductor Components Industries, LLC, 2006
1
December, 2006 - Rev. 0
Publication Order Number: NCP5030/D
NCP5030
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 Iout = 300 mA
Figure 2. Efficiency vs. Vin Voltage
Vbat 10 mF X5R 0805 6.3 V C1 1 mF VIN 10 PVIN 4 C2 4.7 mH L1
LX1
5/6
LX2
7 VOUT Up to 900 mA 22 mF X5R 1206 6.3 V
Osc 700 kHz PCA 12 R1 39 k 3 CTRL 250 K Bandgap
Thermal Shutdown
8
C3 PWM CONTROLLER 9 VS
LED
AGND
11
FB 200 mV
1
2
COMP R2 100 k C5 330 pF
PGND
13
C4 22 pF
R3 220 m
Figure 3. Simplified Block Diagram
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NCP5030
PIN FUNCTION DESCRIPTION
Pin 1 Name FB Type INPUT Description Feedback: Reference voltage is 200 mV. The cathode of the LED and a resistor to ground to set the LED current should be connected at this point. A "5% metal film resistor, or better, is recommended for best output accuracy. An analog signal can be applied to this input to dim the LED. Loop Compensation: A frequency compensation network must be connected between this pin to the ground to ensure the stability of the closed loop. See "loop compensation" guidelines. Control and Enable: An active High logic level on this pin enables the device. A built-in pulldown resistor disables the device if the input is left open. This pin can also be used to control the average current into the load by applying a low frequency PWM signal. If a PWM signal is applied, the frequency should be high enough to avoid optical flicker, but be no greater than 1.0 kHz. Power Voltage Input Supply: A 10 mF ceramic capacitor or larger must bypass this input to the ground. This capacitor should be placed as close a possible to this input. Switch LX1: Both pins are connected to the input node of the H-bridge. The inductor should be connected between this node and LX2. The recommended inductor size is 4.7 mH. Switch LX2: This pin is connected to the opposite node of the H-bridge and the power inductor is connected between this node and LX1. Power Output: A filter capacitor is necessary on this pin for the stability of the loop, to smooth the current flowing into the load, and to limit the noise created by the fast transients present in this circuitry. A 22 mF ceramic capacitor bypass to GND or larger is recommended. For White LED applications, this pin is also connected to the anode of the LED. Care must be observed to avoid EMI through the PCB copper tracks connected to this pin. Voltage Sense: This pin must be connected to COUT with a dedicated track to minimize serial parasitic inductor and to sense VOUT with high accuracy. This pin supplies some of the NCP5030 internal blocks when the voltage is higher than VIN. Supply Pin: This pin supplies the internal control circuitry and must be connected to PVIN. Recommended bypass capacitor is 1.0 mF ceramic or larger. Analog Ground: This pin is the system ground and carries the analog signals. This pin must be connected to the ground plan like PGND. Peak Current Adjust: A resistor between this input and ground controls the maximum peak current allowed in the inductor. The minimum value for this resistor is 30 kW. Increasing this value decreases the peak current. This allows the user to adjust the current based on the application needs and scale the size of the inductor accordingly. See "Switch Current Limit"guidelines in application section. Power Ground: This pin is the power ground for NCP5030 and carries the switching current. Care must be observed to avoid high-density current flow in a limited PCB copper track.
2 3
COMP CTRL
INPUT INPUT
4 5/6 7 8
PVIN LX1 LX2 VOUT
POWER POWER POWER POWER
9
VS
POWER
10 11 12
VIN AGND PCA
POWER POWER INPUT
13
PGND
POWER
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NCP5030
MAXIMUM RATINGS (Note 1)
Rating Power Supply Voltage (Note 2) Over Voltage Protection Human Body Model (HBM) ESD Rating (Note 3) Machine Model (MM) ESD Rating (Note 3) Digital Input Voltage Digital Input Current WDFN 3x4 Package Power Dissipation @ TA = +85C (Note 5) Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Moisture Sensitivy Level (Note 7) Symbol Vbat Vout ESD HBM ESD MM CTRL Value 7.0 6.5 2.0 200 -0.3 < Vin < Vbat + 0.3 1.0 Internally Limited 6.0 (Note 6) -40 to +85 -40 to +125 +150 -65 to +150 1 Unit V V kV V V mA W C/W C/W C C C C
PD RqJC RqJA TA TJ TJMAX Tstg MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25C. 2. According to JEDEC standard JESD22-A108B. 3. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22-A114 for all pins Machine Model (MM) "200 V per JEDEC standard: JESD22-A115 for all pins 4. Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78. 5. The thermal shutdown set to 160C (typical) avoids irreversible damage on the device due to power dissipation. 6. For the 12-Pin 3x4 WDFN Package, the RqJA is highly dependent on the PCB heat-sink area. For example, RqJA can be 57C/W for a one layer board and 43 for a four layer board. 7. Per IPC/JEDEC standard: J-STD-020A.
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NCP5030
ELECTRICAL CHARACTERISTICS (Limits apply for TA between -40C to +85C and Vin = 3.6 V unless otherwise noted.)
Characteristic Operational Power Supply Maximum Inductor Current (Note 11) (See Figure 8) Switches P1 and P2 ON Resistance Switches N1 and N2 ON Resistance Switches P1 and P2 Leakage Current Switches N1 and N2 Leakage Current Internal Oscillator Frequency (Note 8) Efficiency (Notes 9, 10 and 11) Output Voltage Range (Note 11) VOUT-VIN Threshold to Change Mode from Boost to Buck-Boost VIN-VOUT Threshold to Change Mode from Buck-Boost to Buck Threshold to Change Mode Hysteresis Available Output Power (Note 11) When Vin 3.1 V (Vout = 4.7 V, 900 mA) Feedback Voltage Threshold in Steady State at 25C Line Regulation, Measured on FB Pin (Note 8) From DC to 100 Hz and RFB = 1 W Feedback Input Current Standby Current at IOUT = 0 mA, CTRL = Low, Vbat = 4.2 V Quiescent Current Switching at IOUT = 0 mA, CTRL = High, Vbat = 4.2 V (Note 12) VIN Undervoltage Lockout Threshold to Enable the Converter Undervoltage Lockout Hysteresis Soft-start Time (Note 11) Limit of CTRL pin PWM Dimming Frequency (Note 11) Thermal Shutdown Protection Thermal Shutdown Protection Hysteresis Voltage Input Logic Low Voltage Input Logic High CTRL Pin Pulldown Resistance Symbol VIN IPEAK_MAX PMOS RDSON NMOS RDSON PMOS L NMOS L FOSC EFF VOUT TBOOST TBUCK HMODE POUT 4.3 FBV FBVLR FBC ISTB IQS UVLO 2.2 UVLOH SST FDIM TSD TSDH VIL VIH RCTRL - - - - - - 1.2 150 2.4 100 1000 0.2 160 20 - - 220 2.6 - - - - - 0.4 - 290 mV ms kHz C C V V kW 190 - - - - - 200 5.0 - 0.3 5.0 - 210 - 0.1 3.0 - mV mV/V mA mA mA V Min 2.7 -20% - - - - 600 - 2.2 - - - Typ - 4.0 100 100 0.5 0.5 700 85 - 375 650 100 Max 5.5 +20% - - - - 800 - 5.5 - - - Unit V A mW mW mA mA MHz % V mV mV mV W
8. TA between -10C to +85C 9. Efficiency is defined by 100 * (Pout/Pin) at 25C. Vin = 3.3 V, IOUT = 500 mA, Load = 1 LED (Vf = 3.9 V) 10. L = 4.7 mH (TDK RLF7030T-4R7M3R4), Cout = 22 mF X5R 11. Guaranteed by design and characterized. 12. The overall tolerance is dependent on the accuracy of the external resistor.
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NCP5030
TYPICAL PERFORMANCE CHARACTERISTICS
100 95 90 85 EFF (%) 80 75 70 65 60 55 50 2.5 3.0 3.5 Efficiency = 100 X (PLED/PIN) 4.0 VIN (V) 4.5 5.0 5.5 900 mA 100 mA 400 mA
Figure 4. Efficiency vs. VIN LED = Lumileds LUXEON III, L = TDK RLF7030T-4R7
100 Vin = 3.9 V 90 Vin = 4.5 V EFF (%) EFF (%) 80 Vin = 5.5 V 80 Vin = 4.4 V 70 Vin = 4.0 V 60 50 0 100 200 300 400 500 600 700 800 900 Iout (mA) 60 50 0 100 200 300 400 500 600 700 800 900 Iout (mA) Vin = 3.4 V 90 100
70
Figure 5. Buck Mode Efficiency vs. IOUT @ VOUT = 3.1 V L = TDK RLF7030T-4R7
100 Vin = 4.1 V 90 IPEAK(max) (A) Vin = 3.6 V Vin = 3.1 V 70 4.0 3.5 3.0
Figure 6. Buck-Boost Mode Eff. vs. IOUT @ VOUT = 3.8 V L = TDK RLF7030T-4R7
Vin = 3.6 V 2.5 2.0 1.5 1.0 0.5
EFF (%)
80
60 50 0 100 200 300 400 500 600 700 800 900 Iout (mA)
0 10 100 RPCA (kW) 1000
Figure 7. Boost Mode Efficiency vs. IOUT @ VOUT = 5.0 V L = TDK RLF7030T-4R7
Figure 8. IPEAK_MAX vs. RPCA
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NCP5030
TYPICAL PERFORMANCE CHARACTERISTICS
150 150
Vin = 2.7 V Vin = 3.1 V (mW) (mW) 100 Vin = 4.2 V Vin = 3.6 V 100 Vin = 3.6 V Vin = 3.1 V
Vin = 2.7 V
Vin = 4.2 V
50 -40
-20
0
20
40
60
80
100
50 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 9. NMOS RDSON vs. Temperature
Figure 10. PMOS RDSON vs. Temperature
Figure 11. Transitional Period Switch Pins (LX1 and LX2) from Boost to Buck-Boost when VOUT - VIN is < than 375 mV
730 720 710 700 690 680 670 660 650 640 630 620 610 600 -50 210
Figure 12. Transitional Period Switch Pins (LX1 and LX2) from Buck to Buck-Boost when VIN - VOUT is > than 650 mV
FEEDBACK VOLTAGE -25 0 25 50 75 100 125
FREQUENCY (kHz)
205
200
195
190 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. Oscillator Frequency vs. Temperature VOUT = 3.6 V, VIN = 3.6 V
Figure 14. Feedback Voltage vs. Temperature VOUT = 3.6 V, VIN = 3.6 V
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NCP5030
DETAILED OPERATING DESCRIPTION
VBat 2.7 to 5.5 V PVIN 4 Cin 10 mF 4.7 mH 30 mW
VIN 10 1.18 V PCA RPCA 39 K 12 I_SENSE SENSE SENSE CURRENT 1000 mV Bandgap Reference and Current Sources VIN
LX1 5/6
LX2 7 8 VOUT Cout 22 mF 9 VS
P1
P2
N1 THERMAL PROTECTION
N2 D1
IPEAK_REF
VIN VS - + I_PMAX I_SENSE IPEAK COMP MODE DETECTION
LOGIC AND ANTICROSS- CONDUCTION
CONSTANT TOFF 300 ns OVP COMP PWM OVP DISABLE + - OVP REF
+ -
RST
PWM COMP
ONE SHOT VIN CLOCK UVLO REF
SET
- +
UVLO COMP UVLO ERROR AMP FB
- + SOFT START 200 mV
1
220 m R_SENSE
RAMP COMP
OSC 700 kHz 220 k
2
COMP 100 k
AGND
11
13
EXPOSED PAD PGND ENABLE
3 CTRL
22 pF
330 pF
Figure 15. Functional Block Diagram
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NCP5030
Operation The NCP5030 DC-DC converter is based on a Current Mode PWM architecture specifically designed to efficiently provide a regulated current to a high current white LED. This device utilizes fixed frequency synchronous buck-boost switching regulator architecture. This topology is critical in single cell Lithium-Ion/ Polymer battery or 3 Alkaline powered applications as the forward voltage of the LED may be greater than or less than the battery voltage. A low feedback voltage of 200 mV (nom) minimizes power losses in the current setting resistor connected between the cathode of the LED and ground. The core switching regulator is configured as a full bridge with four low RDSON (0.1 W) MOSFET switches to maximize efficient power delivery. Another advantage of this topology is that it supports a true-shut down mode where the LED will be disconnected from the power supply when the device is placed in disable mode. Figure 16 shows how the four switches are connected to charge and discharge the current from PVIN to VOUT through the inductor.
VIN IIN IOUT VOUT
The internal oscillator provides a 700 kHz clock signal to trigger the PWM controller on each rising edge (SET signal) which starts a cycle. In pure buck or boost mode, the converter operates in two-phase mode, the first one to charge the inductor, followed by a synchronous rectifier discharge phase. However, in buck-boost mode, to get high efficiency the converter controls the switches in three separate phases (see Buck-Boost Mode Section). The capacitor COUT is used to store energy from the inductor to smooth output voltage thus constantly powering the load.
Buck Mode (VOUT < VIN - 650 mV)
In Buck mode, switches P1 and N1 are toggling and the two others are fixed, the switch N2 is all time OFF and the switch P2 is all time ON. The buck converter operates in two separate phase (See Figure 18). The first one is TON when IIN = IOUT. During this phase the switch P1 is ON, N1 is OFF and the current increases through the inductor. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMP compares the output of the adder and the signal from ERROR AMP. When the comparator threshold is exceeded, TON phase is followed by TOFF. P1 switch is turned OFF and N1 is ON until next clock rising edge. The current is only delivered by the inductor, which means that IIN = 0
P1 L LX1
P2 LOAD
LX2 COUT
Start Cycle LX1
N1
N2
LX2
LX2 = VOUT
Figure 16. Basic Power Switches Topology
The converter operates in three different modes as a function of VOUT - VIN (Figure 17): In Buck mode when VOUT is below VIN - 650 mV (TBUCK nominal), in Boost mode when VOUT is above VIN + 375 mV (TBOOST nominal) and in Buck-Boost mode when VOUT is between this tow thresholds.
VIN VOUT
1.43 mS IL TON TOFF
Ipeak Ivalley
IOUT Buck 2- Phase Buck-Boost 3- Phase TBOOST Boost 2- Phase TBUCK
Figure 18. Basic DC-DC Buck Operation Boost Mode (VOUT > VIN + 375 mV)
Figure 17. Conversion Mode
The switches in boost mode are inversely controlled than in buck mode. Switches P2 and N2 are toggling and the two others are fixed. Switch P1 is all time ON and the switch N1 is all time OFF. The boost converter operates in two separate phases (See Figure 19). The first one is TON when
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NCP5030
the inductor is charged by current from the battery to store up energy. During this phase the switch N2 is on and P2 is off. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMP compares the output of the adder and the signal from ERROR AMP. When the comparator threshold is exceeded, the flip-flop circuit is reset, P2 switch is turned on, and N2 is off until the rising edge of the next clock cycle.
LX1
VIN Start Cycle
LX2 VOUT 1.43 mS Ipeak Ivalley
LX1
LX1 = VIN
IL
TON TOFF
TC
LX2
Start Cycle IOUT 1.43 mS Ipeak
IL TON TOFF
Figure 20. Basic DC-DC BB Operation
Ivalley
In addition, there are four safety circuits like OVP, UVLO, IPEAK COMP, THERMAL PROTECTION, which can disable the DC-DC conversion.
Error Amp and Compensation
IOUT
Figure 19. Basic DC-DC Boost Operation Buck-Boost Mode (VIN - 650 mV < VOUT < VIN + 375 mV)
Figure 20 shows the basic DC-DC Buck-Boost operation. Now, all four switches are running and the controller operates in three separate phases to reach higher efficiency. The first step is TON when the inductor is charged by current from the battery. During this phase the switch P1_N2 are on and P2_N1 are off. Like the other modes, the current measured by SENSE CURRENT is added to the RAMP COMP signal and compared by PWM COMP with the signal from ERROR AMP. When PWM COMP threshold is exceeded, the flip-flop circuit is reset and the controller switches in TOFF phase. In this second phase, the switch P1_N2 are off and P2_N1 are ON. Because time of TOFF phase is constant, the current stored in the inductor during 250 ns (nominal) is drained to VOUT. After this, CONSTANT TOFF delay is over, the circuit logic switches in the third phase named TC (Time Conduction) where the inductor is directly connected from PVIN to VOUT. The switch P1_P2 are on and switches N_N2 are off until the rising edge of the next clock cycle.
Regulation loop is closed by the error amplifier, which compares the feedback voltage with the reference set at 200 mV. Thanks to the transconductance structure, the compensation network is directly connected to the error amplifier output. This external passive network is necessary to sets the dominant pole to gets a good loop stability. The compensation network shown in Figure 21 provides a phase margin greater than 45 whatever the current drives in a white LED load.
COMP 100 k 22 pF 330 pF
Figure 21. Compensation Network LED Current Selection
The feedback resistor (RSENSE) determines the LED current in steady state. The control loop regulates the current in such a way that the average voltage at the FB input is 200 mV (nominal). For example, should one need 800 mA output current, RSENSE should be selected according to the following equation:
F RSENSE + BV + 200 mV + 250 mW ILED 800 mA
(eq. 1)
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NCP5030
Current Selection
Figure 22 shows an application schematic to drive two selected currents I1 and I2.
ILED + I1 ) I2
(eq. 2)
VOUT LED PGND VS NCP5030 RSENSE 200 mV R2 FLASH/TORCH NTHS5404 I2 M1 R1 I1
Because of the soft-start function set at 1000 ms (nominal), higher frequency would cause the device to remain active with lower than expected brightness. Nevertheless, in this case a dimming control using a filtered PWM signal can be used. In addition, for DC voltage control the same technique is suitable and the filter is taken away. Please refer to "NPC5030 Dimming Control Application Note".
Inductor Selection
Figure 22. Two Current Selections
Three main electrical parameters need to be considered when choosing an inductor: the value of the inductor, the saturation current and the DCR. Firstly, we need to check if the inductor is able to handle the peak current without saturating. Therefore, we have to consider that the maximum peak inductor current is in Buck-Boost mode when VOUT is closed TBOOST threshold for the lower operating VIN. Obviously, the peak current inductor is higher when this device supplies the maximum required current. In this case, the DC-DC converter is supposed to operate in Continuous Conduction Mode (CCM) so the dotted curve in Figure 23 gives the inductor peak current as a function of load current:
2.5 Switch Current Limit Setup by RPCA
An active low logic level of M1 enables the low current mode, So I2 = 0 and I1 = ILED = 200 mV / R1. For example, should one need 200 mA for low current mode and 800 mA for high current mode, R1 should be selected according to the following below:
Ipeak (A)
FB
2
F R1 + BV + 200 mV + 1.0 W I1 200 mA
(eq. 3)
1.5
So an active high logic level M1 on gate enables the high current mode then IFLASH = I1 + I2 and according Equation 2 and 3, R2 should be selected regarding the following equation:
FBV R2 + * RDSON_M1 IFLASH * I1 200 mV R2 + * 33 mW 800 mA * 200 mA R2 + 300 mW
(eq. 4)
1 Operating Inductor Peak Current 0.5 0 100
200
300
400
500 Iout (mA)
600
700
800
900
Figure 23. Inductor Peak Currents Vs. IOUT (mA)
Some recommended resistors include, but are not limited to: PANASONIC ERJ3BQF1R0V (1.0 W 1% 0603) PANASONIC ERJ3BQFR30V (300 mW 1% 0603) PANASONIC ERJ3BQJ1R0V (1.0 W 5% 0603) PANASONIC ERJ3BQJR30V (300 mW 5% 0603)
Analogue Dimming
Finally, an acceptable DCR must be selected regarding losses in the coil and must be lower than 100 mW to limit excessive voltage drop. In addition, as DCR is reduced, overall efficiency will improve. Some recommended inductors are included but are not limited to: TDK VLF5014AT-4R71R1 TDK RLF7030T-4R7M3R4 COPPER BUSSMANN FP3-4R7 MURATA LQH43CN4R7M03L NIC: NIP16W4R7MTRF
Switch Current Limit
In white LED applications, it is desirable to operate the LEDs at a specific operating current, as the color shift as the bias current. As a consequence, it is recommended to dim the LED current by Pulse Width Modulation techniques. A low frequency PWM signal can be applied to the CTRL input. LED brightness can be changed by varying the duty cycle. To avoid any optical flicker the frequency must be higher than 100 Hz and preferably less than 300 Hz.
This safety feature is clamping the maximum allowed current in the inductor according to external RPCA resistor, which is connected between PCA input and the ground. This allows the user to reduce the peak current being drawn
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NCP5030
from the supply according to the application's specific requirements. The Ipeak maximum value is 4 A, resulting in a minimum resistor value of 30 kW. Please refer to Figure 8 IPEAK_MAX Vs RPCA page 6 to choose RPCA value versus IPEAK_MAX. By limiting the peak current to the needs of the application, the inductor sizing can be scaled appropriately to the specific requirements. This allows the PCB footprint to be minimized.
Input and Output Capacitors Selection Under Voltage Lock Out
To ensure proper operation under low input voltage conditions, the device has a built-in Under-Voltage Lock Out (UVLO) circuit. The device remains disabled until the input voltage exceeds 2.35 V (nominal). This circuit has 100 mV hysteresis to provide noise immunity to transient conditions.
Thermal Protection
COUT stores energy during the TOFF phase and sustains the load current during the TON phase. In order ensure the loop stability and minimize the output ripple, at least 22 mF low ESR multi-layer ceramic capacitor type X5R is recommended. The VIN and PVIN input pin need to be bypassed by a X5R or an equivalent low ESR ceramic capacitor. Near the PVIN pin at least 10 mF 6.3 V or higher ceramic capacitor is needed. Regarding VIN pin a 1 mF 6.3 V close to the pad is sufficient. Some recommended capacitors include but are not limited to: 22 mF 6.3 V 0805 TDK: C2012X5R0J226MTJ 22 mF 6.3 V 1206 MURATA: GRM31CR60J226KE19L 10 mF 6.3 V 0805 TDK C2012X5R0J106MT
Over Voltage Protection (OVP)
Normal operation of the NCP5030 is disabled to protect the device if the junction temperature exceeds 160C. When the junction temperature drops below 140C, normal operation will resume.
Layout Recommendations
As with all switching DC/DC converter, care must be observed to the PCB board layout and component placement. To prevent electromagnetic interference (EMI) problems and reduce voltage ripple of the device any copper trace, which see high frequency switching path, should be optimized. So the input and output bypass ceramic capacitor, CIN and COUT as depicted in Figure 24 must be placed as close as possible the NCP5030 and connected directly between pins and ground plane. In additional, the track connection between the inductor and the switching input, SW pin must be minimized to reduce EMI radiation.
The NCP5030 regulates the load current. If there is an open load condition such as a lost connection to the White LED, the converter keeps supplying current to the Cout capacitor causing the output voltage to rise rapidly. To prevent the device from being damaged and to eliminate external protection components such as zener diode, the NCP5030 incorporates an OVP circuit, which monitors the output voltage with a resistive divider network and a comparator and voltage reference. If the output reaches 6 V (nominal), the OVP circuit will detect a fault and inhibit PWM operation. This comparator has 200 mV hysteresis to allow the PWM operation to resume automatically when the load is reconnected and when the voltage drops below 5.8 V.
TBD
Figure 24. Recommended PCB Layout
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NCP5030
ORDERING INFORMATION
Device NCP5030MTTXG Package WDFN12, 3x4 mm (Pb-Free) Shipping 3000/T ape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Demo Board Available:
The NCP5030EVB/D evaluation board that configures the device to drive high current through one white LED.
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NCP5030
PACKAGE DIMENSIONS
WDFN12, 3x4, 0.5P CASE 506AY-01 ISSUE O
D A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 4.00 BSC 3.20 3.40 3.00 BSC 1.60 1.80 0.50 BSC 0.20 --- 0.30 0.50
B
PIN 1 INDEX AREA
2X
0.10 C
2X
0.10 C
0.10 C
12X
0.08 C
12X
K
12X
L BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5030/D

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